?002 fairchild semiconductor corporation RFD10P03L, RFD10P03Lsm, rfp10p03l rev. b RFD10P03L, RFD10P03Lsm, rfp10p03l 10a, 30v, 0.200 ohm, logic level, p-channel power mosfet these products are p-channel power mosfets manufactured using the megafet process. this process, which uses feature sizes approaching those of lsi circuits, gives optimum utilization of silicon, resulting in outstanding performance. they were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. these transistors can be operated directly from integrated circuits. formerly developmental type ta49205. features 10a, 30v ? ds(on) = 0.200 ? temperature compensating pspice model pspice thermal model peak current vs pulse width curve uis rating curve 175 o c operating temperature symbol packaging ordering information part number package brand RFD10P03L to-251aa 10p03l RFD10P03Lsm to-252aa 10p03l rfp10p03l to-220ab f10p03l note: when ordering, use the entire part number. add the suf?, 9a, to obtain the to-252aa variant in tape and reel, i.e. RFD10P03Lsm 9a.. g d s jedec to-251aa jedec to-252aa jedec to-220ab source drain (flange) gate drain gate source drain (flange) gate drain (flange) source drain data sheet january 2002
?002 fairchild semiconductor corporation RFD10P03L, RFD10P03Lsm, rfp10p03l rev. b absolute maximum ratings t c = 25 o c unless otherwise speci? RFD10P03L, RFD10P03Lsm, rfp10p03l units drain to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss -30 v drain to gate voltage (r gs = 20k ?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr -30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 10 v drain current rms continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 10 see figure 5 a single pulse avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as refer to uis curve power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 0.43 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum lead temperature for soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l (0.063in (1.6mm) from case for 10s) 300 o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 11) -30 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 12) -1 - -2 v zero gate voltage drain current i dss v ds = -30v, t c = 25 o c---1 a v gs = 0v t c = 150 o c - - -50 a gate to source leakage current i gss v gs = 10v - - 100 na drain to source on resistance (note 1) r ds(on) i d = 10a, v gs = -5v (figures 9, 10) - - 0.200 ? i d = 10a, v gs = -4.5v (figures 9, 10) 0.220 ? turn-on time t on v dd = 15v, i d ? 10a, r l = 1.5 ? , r gs = 5 ?, v gs = -5v (figure 13) - - 100 ns turn-on delay time t d(on) -15- ns rise time t r -50- ns turn-off delay time t d(off) -35- ns fall time t f -20- ns turn-off time t off - - 80 ns total gate charge q g(tot) v gs = 0 to -10v v dd = -24v, i d ? 10a, r l = 2.4 ? i g(ref) = -0.25ma (figure 14) -2530nc gate charge at -5v q g(-5) v gs = 0 to -5v - 13 16 nc threshold gate charge q g(th) v gs = 0 to -1v - 1.2 1.5 nc input capacitance c iss v ds = -25v, v gs = 0v, f = 1mhz (figure 15) - 1035 - pf output capacitance c oss - 340 - pf reverse transfer capacitance c rss -35-pf thermal resistance, junction to case r jc - - 2.30 o c/w thermal resistance, junction to ambient r ja RFD10P03L, RFD10P03Lsm - - 100 o c/w rfp10p03l 80 o c/w source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain forward voltage v sd i sd = -10a - - -1.5 v reverse recovery time t rr i sd = -10a, di sd /dt = -100a/ s--75ns note: 2. pulse test: pulse width 300 s, duty cycle 2%. RFD10P03L, RFD10P03Lsm, rfp10p03l
?002 fairchild semiconductor corporation RFD10P03L, RFD10P03Lsm, rfp10p03l rev. b typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. forward bias safe operating area figure 5. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 -4 -2 0 25 50 75 100 125 150 -8 i d , drain current (a) t c , case temperature ( o c) -12 -6 175 -10 t, rectangular pulse duration (s) 10 1 z jc , normalized thermal impedance 10 -3 10 -2 10 -1 10 0 10 -5 10 -4 1.0 0.01 0.1 notes: duty factor: d = t 1 /t 2 p dm t 1 t 2 0.1 0.02 0.2 0.5 0.01 0.05 single pulse 2.0 peak t j = p dm x z jc x r jc + t c -100 -10 -1 -1 -10 -100 v ds , drain to source voltage (v) i d , drain current (a) operation in this area may be limited by r ds(on) v dss max = -30v 100ms dc t j = max rated t c = 25 o c 10ms 1ms 100 s 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 -10 t, pulse width (s) i dm , peak current capability (a) v gs = -10v v gs = -5v transconductance may limit current in this region for temperatures above 25 o c derate peak current capability as follows: -5 ii 25 175 t c 150 ----------------------- - ?? ?? ?? = t c = 25 o c -100 RFD10P03L, RFD10P03Lsm, rfp10p03l
?002 fairchild semiconductor corporation RFD10P03L, RFD10P03Lsm, rfp10p03l rev. b note: refer to fairchild application notes an9321 and an9322. figure 6. unclamped inductive switching capability figure 7. saturation characteristics figure 8. transfer characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature figure 11. normalized drain to source breakdown voltage vs junction temperature typical performance curves unless otherwise speci?d (continued) -50 -10 -1 0.01 0.1 1 10 t av , time in avalanche (ms) i as , avalanche current (a) if r 0 t av = (l/r) ln [(i as *r)/(1.3 rated bv dss - v dd ) + 1] starting t j = 150 o c starting t j = 25 o c t av = (l) (i as )/(1.3 rated bv dss - v dd ) if r = 0 0 0-1 -2 -3 -5 -10 i d , drain current (a) v ds , drain to source voltage (v) v gs = -10v -4 -20 -15 -25 -5 pulse duration = 250 s t c = 25 o c duty cycle = 0.5% max v gs = -4v v gs = -3.5v v gs = -3v v gs = -5v 0 -3.0 -4.5 -6.0 -1.5 0 -10 175 o c i d(on) , on-state drain current (a) v gs , gate to source voltage (v) -55 o c 25 o c -20 -25 -15 -5 pulse duration = 250 s duty cycle = 0.5% max v dd = -15v r ds(on), drain to source 0 100 200 300 400 -2 -4 -6 -8 -10 v gs , gate to source voltage (v) i d = -20a i d = -10a i d = -5a i d = -2.5a on resistance (m ? ) pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c normalized drain to source 2.0 0.5 0 -40 0 40 t j , junction temperature ( o c) 120 1.0 80 1.5 160 200 -80 v gs = -5v, i d = -10a on resistance pulse duration = 80 s duty cycle = 0.5% max normalized drain to source 1.2 1.0 0.9 0.8 -40 0 40 t j , junction temperature ( o c) 120 1.1 80 breakdown voltage -80 160 200 i d =- 250ua RFD10P03L, RFD10P03Lsm, rfp10p03l
?002 fairchild semiconductor corporation RFD10P03L, RFD10P03Lsm, rfp10p03l rev. b figure 12. normalized gate threshold voltage vs junction temperature figure 13. switching time vs gate resistance note: refer to fairchild application notes an7254 and an7260. figure 14. normalized switching waveforms for constant gate current figure 15. capacitance vs drain to source voltage test circuits and waveforms figure 16. unclamped energy test circuit figure 17. unclamped energy waveforms typical performance curves unless otherwise speci?d (continued) -80 -40 0 40 80 120 160 0.4 0.8 1.0 1.2 normalized gate threshold voltage t j , junction temperature ( o c) 200 v gs = v ds , i d = -250 a 0.6 125 20 30 40 50 0 25 100 150 50 0 10 switching time (ns) r gs , gate to source resistance ( ? ) t d(off) t d(on) t r t f 75 v dd = -15v, i d = -10a, r l = 1.50 ? -30 -22.5 -15 -7.5 0 -5.00 -3.75 -2.50 -1.25 0.00 20 i g(ref) i g(act) 80 i g(ref) i g(act) t, time ( s) v dd = bv dss r l = 3.0 ? i g(ref) = -0.25ma 0.75 bv dss 0.50 bv dss 0.25 bv dss 0.75 bv dss 0.50 bv dss 0.25 bv dss v ds , drain to source voltage (v) v gs , gate to source voltage (v) v gs = -5v v dd =bv dss 800 600 400 200 0 0 -5 -10 -15 -20 -25 c, capacitance (pf) v ds , drain to source voltage (v) 1200 c iss c oss c rss 1000 v gs = 0v, f = 0.1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd t p 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v gs v dd v ds bv dss t p i as t av 0 RFD10P03L, RFD10P03Lsm, rfp10p03l
?002 fairchild semiconductor corporation RFD10P03L, RFD10P03Lsm, rfp10p03l rev. b figure 18. switching time test circuit figure 19. resistive switching waveforms figure 20. gate charge test circuit figure 21. gate charge waveforms test circuits and waveforms (continued) v gs r l r g dut + - v dd t d(on) t r 90% 10% v ds 90% t f t d(off) t off 90% 50% 50% 10% pulse width v gs t on 10% 0 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = -1v q g(-5) v gs = -5v q g(tot) v gs = -10v v ds -v gs i g(ref) 0 0 RFD10P03L, RFD10P03Lsm, rfp10p03l
?002 fairchild semiconductor corporation RFD10P03L, RFD10P03Lsm, rfp10p03l rev. b pspice electrical model .subckt RFD10P03L 2 1 3 rev 22 aug 96 ca 12 8 1.29e-9 cb 15 14 9.90e-10 cin 6 8 1.01e-9 dbody 5 7 dbodymod dbreak 7 11 dbreakmod dplcap 10 6 dplcapmod ebreak 5 11 17 18 -36.49 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 5 10 8 6 1 evthres 6 21 19 8 1 evtemp 6 20 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 3.40e-9 lsource 3 7 3.22e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 68.25e-3 rgate 9 20 2.54 rscl1 5 51 rsclmod 1e-6 rscl2 5 50 1e3 rsource 8 7 rsourcemod 25.00e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 escl 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*33),5.0))} .model dbodymod d (is=9.15e-13 rs=3.25e-2 ikf=0.05 n=0.97 trs1=4.11e-5 trs2=2.03e-6 cjo=1.13e-9 m=0.40 tt=3.72e-8) .model dbreakmod d ( rs=2.62e-1 trs1=1.74e-3 trs2=-3.81e-6) .model dplcapmod d (cjo=1.46e-10 is=1e-30 n=10 m=0.50) .model mstrongmod pmos (vto=-1.95 kp=11.60 is=1e-30 n=10 tox=1 l=1u w=1u) .model mmedmod pmos (vto=-1.65 kp=1.00 is=1e-30 n=10 tox=1 l=1u w=1u rg=2.54) .model mweakmod pmos (vto=-1.43 kp=0.09 is=1e-30 n=10 tox=1 l=1u w=1u rg=25.4 rs=0.1) .model rbreakmod res (tc1=9.17e-4 tc2=-2.74e-7) .model rdrainmod res (tc1=6.35e-3 tc2=1.98e-5) .model rsourcemod res (tc1=0 tc2=0) .model rsclmod res (tc1=2e-3 tc2=0) .model rvthresmod res (tc1=1.23e-3 tc2=1.97e-6) .model rvtempmod res (tc1=-1.18e-3 tc2=1.44e-6) .model s1amod vswitch (ron=1e-5 roff=0.1 von=4.80 voff=1.80) .model s1bmod vswitch (ron=1e-5 roff=0.1 von=1.80 voff=4.80) .model s2amod vswitch (ron=1e-5 roff=0.1 von=-0.40 voff=-3.40) .model s2bmod vswitch (ron=1e-5 roff=0.1 von=-3.40 voff=-0.40) ends for further discussion of the pspice model consult a new pspice sub-circuit for the power mosfet featuring global temperature options; authored by william j. hepp and c. frank wheatley. 18 22 - + + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 8 6 ebreak 6 RFD10P03L, RFD10P03Lsm, rfp10p03l
?002 fairchild semiconductor corporation RFD10P03L, RFD10P03Lsm, rfp10p03l rev. b pspice thermal model rev 29 aug 96 rfp10p03l ctherm1 7 6 5.00e-7 ctherm2 6 5 5.35e-4 ctherm3 5 4 5.50e-4 ctherm4 4 3 1.75e-3 ctherm5 3 2 1.25e-2 ctherm6 2 1 0.45 rtherm1 7 6 1.00e-2 rtherm2 6 5 2.05e-2 rtherm3 5 4 5.39e-2 rtherm4 4 3 5.45e-1 rtherm5 3 2 1.01 rtherm6 2 1 0.50 RFD10P03L, RFD10P03Lsm ctherm1 7 6 5.00e-7 ctherm2 6 5 5.35e-4 ctherm3 5 4 5.50e-4 ctherm4 4 3 1.75e-3 ctherm5 3 2 1.25e-2 ctherm6 2 1 0.11 rtherm1 7 6 1.00e-2 rtherm2 6 5 2.05e-2 rtherm3 5 4 5.39e-2 rtherm4 4 3 5.45e-1 rtherm5 3 2 1.01 rtherm6 2 1 0.50 rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 1 2 3 4 5 6 7 junction case RFD10P03L, RFD10P03Lsm, rfp10p03l
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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